`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/16 14:00:38
// Design Name: 
// Module Name: reg32
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module regw #(parameter  WIDTH=32)(
    input clk,
    input rst,
    input en,
    input [WIDTH-1:0]  din,
    output [WIDTH-1:0] dout
    );
    reg  [WIDTH-1:0] d_reg;
    always @ (posedge clk)
    begin
        if(rst) d_reg <=  {WIDTH{1'b0}};
        else if(en) d_reg <= din;
    end
assign dout = d_reg;
endmodule
module reg_initw #(parameter  WIDTH=32)(
    input clk,
    input rst,
    input en,
    input [WIDTH-1:0]  init_value,
    input [WIDTH-1:0]  din,
    output  [WIDTH-1:0] dout
    );
    reg  [WIDTH-1:0] d_reg;
    always @ (posedge clk)
    begin
        if(rst) d_reg <=  init_value;
        else if(en) d_reg <= din;
    end
assign dout = d_reg;
endmodule
module notRSreg1(
    input clk,
    input rst,
    input set1,
    input  set0,
    output  dout
);
    wire reg_dout;
    RSreg1 REG(clk,rst,set0,set1,reg_dout);
    assign dout=~reg_dout;
endmodule

module RSreg1(
    input clk,
    input rst,
    input set1,
    input  set0,
    output  dout
    );

    wire en,din;
    assign en=set1|set0;
    assign din=(set1==1)?1:0;
    regw #(.WIDTH(1)) REG(clk,rst,en,din,dout);
endmodule



